1. Field of the Invention
This invention relates to a charge coupled device (hereinafter called CCD) and a method for fabricating the CCD, and, more particularly, to a CCD structure and a method for fabricating the CCD structure, which can induce a maximum potential distribution difference using gate insulation films having different physical properties.
2. Discussion of Related Art
The CCD used in a solid state picture device and a signal delay device transfers signals to a place under adjacent electrodes using a potential difference in the semiconductor induced by potential applied to each of the gate electrodes. Such a CCD is an arrangement of transfer electrodes over a semiconductor substrate separated by a gate insulation film.
Materials used for forming the transfer electrodes are mostly polysilicon doped or injected with high density impurities. The separation between each of the electrodes is a silicon oxide film, an insulating material oxidized in an oxygen or water vapor atmosphere.
A conventional CCD is to be explained with reference to the attached drawings.
FIG. 1 is a section of a conventional CCD. First transfer electrodes 34 are formed by forming a BCCD (Buried CCD) region 32 of a charge transfer region by injecting n type impurity ions into a p type semiconductor substrate 31, overlaying an oxide film 33 over the entire exposed surface, depositing polysilicon on the oxide film 33, and etching the polysilicon in a certain lateral length by a photoetching process.
Barriers 39 are formed on the surface of the BCCD region 32 by ion injection, using the first transfer electrodes 34 as masks. After the first transfer electrodes 34 are insulated with an oxide film, second transfer electrodes 35 are formed of polysilicon between each of the first transfer electrodes 34.
Adjacent first transfer electrodes 34 and second transfer electrodes 35 are applied with first and second clock signals H.phi.1 and H.phi.2, alternatively.
FIGS. 2(a) and 2(b) depict the operating principle of a conventional 2 phase CCD. FIG. 2(a) represents an example of first and second clock signals applied to electrodes of the 2 phase CCD. FIG. 2(b) shows the distribution of potential induced in a semiconductor for the first and second clock pulses to the transfer electrodes and the subsequent transfer process of charges.
At time t=1, the first clock signal H.phi.1 is low, and the second clock signal H.phi.2 is high. A potential well is deepest under the first transfer electrodes 34 to which the second clock signal H.phi.2 is applied, and signal charges are locked up in potential wells under those first transfer electrodes 34.
At time t=2, the first clock signal H.phi.1 is high, and the second clock signal H.phi.2 is low. The deepest potential wells are formed under those first transfer electrodes 34 to which the first clock signal H.phi.1 is applied. The potential wells of the second transfer electrodes 35, which have the second clock signal H.phi.2 applied, are higher, resulting in a charge transfer to the deepest potential wells under those first transfer electrodes 34 which have the first clock signal H.phi.1 applied. At time t=3, the charge transfers are the same as at time t=1.
Transfer of the signal charges are directional, and transfer only to the right side due to the potential barrier formed under the left side electrode in a pair of transfer electrodes. When a series of first and second clock pulses H.phi.1 and H.phi.2 are repeated, there is a transfer of signal charges.
FIG. 3 shows a section of a self align CCD disclosed in U.S. Pat. No. 3,931,674, including a first insulation layer 24, and a second insulation layer 26 formed on a semiconductor substrate 20, an array of conductive films 43, 45, 47, 49 and 51 corresponding to first electrodes arranged at a certain lateral spacing, barrier regions 44, 46, 48 and 50 formed by an ion injection process on parts of the surface of the substrate, and third insulation layers 53 formed on the first electrodes for electric separation of the first electrodes from the second electrodes 84, 86, 88 and 90.
The CCD of FIG. 3 is fabricated by forming the first insulation layer 24, the second insulation layer 26, the first electrodes 43, 45, 47 and 51, and by forming the barrier regions 44, 46, 48 and 50 by injecting impurity ions having a conductive type opposite to the substrate into the surface parts of the semiconductor substrate. When the same voltage is applied to the first electrodes and the adjacent second electrodes 84, 86, 88 and 90, a difference of maximum potential distribution develops due to the difference of impurity density on the surface of the semiconductor under each electrode, and charges are transferred.
Since the conventional art requires an ion injection process for forming barrier regions to induce maximum potential difference at the semiconductor substrate, defects develop inside of the oxide film of the gate insulation film, and at the surface parts of the semiconductor substrate. There is the possibility of degradation of the element characteristics, and to decrease degradation, a complicated process of annealing with heat is required.